The present invention relates to a scan path circuit, an integrated circuit (IC) and an IC checking method, and, more particularly, to those adapted for a large-scale integrated logic circuit. In the present invention, a plurality of scan chain circuits are so connected that input terminals are usable in common, and the common connection is switched to perform an exact test in a short required time by a simplified structure.
With regard to the conventional scan path circuit, a variety of methods have been proposed heretofore for preventing an increase of equipment and a test time caused due to an increase of scan test patterns derived from the enlargement of the logic circuit scale.
More specifically, a scan path circuit is such that a predetermined logic value is set with respect to a logic circuit to be checked, and its response is outputted to an external device. The scan path circuit is formed integrally with the logic circuit to be checked, thereby constituting an integrated circuit. If the scale of the logic circuit to be checked is enlarged, it is unavoidable that the quantity of test patterns also is increased, consequently, prolonging the test time required for each integrated circuit. In case the test time is rendered longer, it becomes necessary to increase the number of testers for ensuring the required number of measurement chips per unit time, hence increasing the equipment correspondingly thereto. And, since such test patters are recorded and held in the memories of testers, the memory capacity needs to be increased in proportion to an increase of the test patterns, thereby causing an increase of the burden to the equipment.
It may be possible to double the number of scan chains by dividing the subject to be checked into a plurality of blocks and setting logic values in parallel simultaneously, and to shorten the required test time by setting scan test patterns in parallel simultaneously. However, this structure increases the number of input terminals for the test patterns and also increases the number of output terminals for the responses, whereby some limits are inevitable practically. And, depending on the kind of testers, the maximum number of handleable scan chains is restricted to 8 through 32 or so, consequently, bringing about limits in increasing the number of scan chains.
As one of the methods proposed for preventing such an increase of the equipment and the test time, a Logic BIST (Built-In Self-Test) system is currently in practical use. According to the Logic BIST system, a scan-in pattern generation circuit for generating test patterns and a scan-out result compression circuit for data-compressing and outputting the responses are formed into an integrated circuit. The scan-in pattern generation circuit consists of, for example, a dummy random pattern generation circuit.
In this system, a logic circuit can be tested merely by supplying clock pulses a predetermined number of times, whereby the tester structure can be simplified correspondingly thereto. Further, it is possible to prevent an increase in the number of terminals while increasing the number of scan chains in the integrated circuit, hence reducing the required test time.
As another method, there is proposed an OP-MISR system which incorporates merely a pattern compressor (MISR: Multiple Input Signature Register) employed in the Logic BIST system. In this OP-MISR system, scan test patterns are inputted from an external device to ensure thereby a high fault detection rate. And, due to data compression of the responses, the tester can be simplified structurally with a reduction of the memory capacity used for the scan-out processing. Further, in the integrated circuit, the number of response output terminals is reduced, and the reduced number of output terminals can be utilized as input terminals for scan test patterns, thereby increasing the number of the scan chains and, consequently, shortening the required test time.
As a further method, there is proposed a Smart BIST system where a decoder for outputting the scan test patterns held after data compression is incorporated instead of the dummy random pattern generator employed in the Logic BIST system. According to this Smart BIST system, the number of scan chains is not limited by the number of terminals, so that the test time can be shortened, and the tester can be structurally simplified by holding the scan test patterns on the integrated circuit side.
In the Logic BIST system, since the scan test patterns are dummy random patterns, there exists a problem that its fault detection rate is lower than the rate in using the conventional scan test patterns.
One method for solving the above problem is proposed in regard to the Logic BIST system. According to this method, a test point is provided in a portion of the logic circuit that is difficult to be tested, and a logic value is set via such a test point or a response is observed therethrough. However, it is reported that, in this method also, a practically sufficient effect has not yet been achieved (ITC INTERNATIONAL TEST CONFERENCE Paper 14.2, pp. 358-367, 1999, “Logic BIST for Large Industrial Designs Real Issues and Case Studies”).
Meanwhile, in the OP-MISR system, a high fault detection rate can be ensured by inputting scan test patterns from an external device; and, the required test time can be shortened by increasing the number of scan chains by utilization of the terminals of the integrated circuit as input terminals for scan test patterns correspondingly to the reduction of the number of response output terminals. However, it is eventually necessary to provide scan test pattern input terminals equal in number to the scan chains, hence causing restrictions in the method of increasing the number of scan chains.
Further, in the Smart BIST system, although the above problems can be solved, the decoder is structurally complicated as the scan test patterns obtained through data compression and held thereafter are decoded by the decoder, so that the integrated circuit is rendered structurally intricate due to the enlargement of the circuit scale and the increase of the chip area.